Synthesis tools for the scheduler circuit #
The scheduler uses the shared circuit synthesis rule (Synthesis.circuit),
shared prefix disjunctions (Synthesis.prefixOr), and two facts about
sorted arrays: a permuted finite array is a reindexing (List.Perm.exists_equiv_ofFn), and in an
array of flags sorted with true flags first, a position holds a true flag exactly when it precedes
the number of true flags (eq_true_iff_lt_card_of_sorted).
Gate counts are synthesis budgets: they count every gate, including constants, and do not certify the running time of any construction.
Main results #
Cslib.Circuits.Synthesis.prefixOr: all prefix disjunctions ofravailable functions.List.Perm.exists_equiv_ofFn: permuted finite arrays differ by a permutation of positions.Cslib.Circuits.Boolean.eq_true_iff_lt_card_of_sorted: positions of true sorted flags.Cslib.Circuits.Boolean.apply_zero_le_of_toLex_le: lexicographic order on one bit.Cslib.Circuits.Boolean.sort_flag_eq_true_iff: positions of true keys after sorting.
References #
- Adapted from MassProduction/Nonuniform/FlagSelection.lean and MassProduction/Nonuniform/OrderedPermutation.lean in S. Schlesinger, Boolean circuit mass production formalization.
Sorting records by a one-bit key with true keys first puts a true key at position j exactly
when j is less than the number of true keys.
The disjunction of the first j + 1 of r functions.
Instances For
All prefix disjunctions of r available functions, sharing each prefix with the next: one OR
gate per function after the first.