Documentation

Complexity.Computability.Circuit.Boolean.MassProduction.Scheduler.Basic

Synthesis tools for the scheduler circuit #

The scheduler uses the shared circuit synthesis rule (Synthesis.circuit), shared prefix disjunctions (Synthesis.prefixOr), and two facts about sorted arrays: a permuted finite array is a reindexing (List.Perm.exists_equiv_ofFn), and in an array of flags sorted with true flags first, a position holds a true flag exactly when it precedes the number of true flags (eq_true_iff_lt_card_of_sorted).

Gate counts are synthesis budgets: they count every gate, including constants, and do not certify the running time of any construction.

Main results #

References #

theorem List.Perm.exists_equiv_ofFn {α : Type u_1} {n : ℕ} {f g : Fin n → α} (h : (ofFn f).Perm (ofFn g)) :
∃ (σ : Equiv.Perm (Fin n)), ∀ (i : Fin n), f i = g (σ i)

Permuted finite arrays differ by a permutation of their positions.

theorem Cslib.Circuits.Boolean.eq_true_iff_lt_card_of_sorted {k : ℕ} (g : Fin k → Bool) (sorted : ∀ (i j : Fin k), i ≤ j → g i = false → g j = false) (j : Fin k) :
g j = true ↔ ↑j < {i : Fin k | g i = true}.card

Every flag is false after a false flag; flags are sorted with true flags first.

On one coordinate, lexicographic order is the order of the bit.

theorem Cslib.Circuits.Boolean.sort_flag_eq_true_iff {α : Type u_1} (φ : α → Fin 1 → Bool) (p : ℕ) (input : Fin (BitonicSort.arity p) → α) (j : Fin (BitonicSort.arity p)) :
φ (BitonicSort.sort (fun (r : α) => toLex (φ r)) p false input j) 0 = true ↔ ↑j < {i : Fin (BitonicSort.arity p) | φ (input i) 0 = true}.card

Sorting records by a one-bit key with true keys first puts a true key at position j exactly when j is less than the number of true keys.

The disjunction of the first j + 1 of r functions.

Instances For
    theorem Cslib.Circuits.Synthesis.prefixOr {n r : ℕ} {s : Set (BooleanFunction n)} (F : Fin r → BooleanFunction n) (hF : ∀ (e : Fin r), F e ∈ s) :

    All prefix disjunctions of r available functions, sharing each prefix with the next: one OR gate per function after the first.