Carry lookahead by parallel prefix doubling #
A carry summary (g, p) acts on a carry c by g || (p && c). Summaries are composed in
significance order. Each round doubles the interval summarized by each cell; cells without a
neighbour retain their summary. The initial carry is an additional cell, so width zero still
has one output: that carry.
The construction uses the associative carry-transfer operation underlying parallel-prefix addition Ladner and Fischer, Section 4. OR-propagate summaries represent the same carry functions. It uses the simple doubling network, rather than their optimized linear-size prefix network. All gates, including constants and negations, count.
Main definitions #
Cslib.Circuits.Boolean.CarryLookahead.combine,Cslib.Circuits.Boolean.CarryLookahead.rangeSummary,Cslib.Circuits.Boolean.CarryLookahead.readRow,Cslib.Circuits.Boolean.CarryLookahead.neighbour: carry-summary composition, interval summaries, row lookup, and cell neighbours at a given distance.Cslib.Circuits.Boolean.CarryLookahead.generateFormula,Cslib.Circuits.Boolean.CarryLookahead.propagateFormula,Cslib.Circuits.Boolean.CarryLookahead.step: the generate/propagate formulas and one prefix-doubling circuit.Cslib.Circuits.Boolean.CarryLookahead.scan: the prefix circuit after a specified number of rounds.Cslib.Circuits.Boolean.CarryLookahead.leftInput,Cslib.Circuits.Boolean.CarryLookahead.rightInput,Cslib.Circuits.Boolean.CarryLookahead.initialGenerate,Cslib.Circuits.Boolean.CarryLookahead.initialPropagate,Cslib.Circuits.Boolean.CarryLookahead.initial: input wire indexing and the initial carry-summary stage.Cslib.Circuits.Boolean.CarryLookahead.carries,Cslib.Circuits.Boolean.CarryLookahead.sumFormula,Cslib.Circuits.Boolean.CarryLookahead.finish,Cslib.Circuits.Boolean.CarryLookahead.inputCarry: the full carry network, sum-bit formulas, output stage, and arithmetic carry specification.Cslib.Circuits.Boolean.carryLookahead: full addition with carry-in and carry-out.Cslib.Circuits.Boolean.carryLookaheadAdd: modular addition of two unsigned words.Cslib.Circuits.Boolean.carryLookaheadFinish: finish a carry-save pair in logarithmic depth.
Main results #
Cslib.Circuits.Boolean.depth_carryLookahead_le_log: logarithmic circuit depth bound.Cslib.Circuits.Boolean.val_eval_carryLookahead: exact unsigned addition at every width.Cslib.Circuits.Boolean.depth_carryLookahead_le,size_carryLookahead: depth at most7 + 2 * clog 2 (w + 1)and exactly15*w + 2*(w+1) + 3*(w+1)*clog 2 (w+1)gates.Cslib.Circuits.Boolean.val_eval_carryLookaheadAdd: addition modulo2^w.Cslib.Circuits.Boolean.pairVal_eval_carryLookaheadFinish_csa4to2_mod: a finishing client for the existing carry-save reduction.
Native polynomial-time generation of the complete codes is proved in CarryLookahead.PolyTime.
References #
The neighbour at the given distance, or the cell itself if the neighbour is absent.
Instances For
After t rounds every cell summarizes the next 2^t original cells, with identity padding.
Each initial generate cell uses a single gate.
Each initial propagate cell uses a single gate.
Each three-way XOR sum-bit formula uses 15 De Morgan gates.
Every gate has fan-in at most two, and the adder has logarithmic depth.
An explicit absolute-constant logarithmic depth bound, including width zero.
A coarse polynomial bound on the complete adder's number of gates.
Each low output bit is the sum bit with the specified incoming carry.
The last output is the final carry, also at width zero.
Exact unsigned addition, including the output carry.
The modular result used to collapse a carry-save pair.
Modular addition adds one constant gate (for the zero carry-in) to carryLookahead.
An explicit absolute-constant depth bound for modular addition.
Polynomial size after fixing the incoming carry and selecting the modular result.
Only one extra constant gate is needed to clear the second carry-save word.
The carry-save finisher has logarithmic depth in the word width.
A polynomial gate bound for the drop-in carry-save finisher.
The replacement finishing stage preserves every carry-save value modulo 2^w.
Every bit of the second output word is false after the logarithmic-depth finisher.
A 4-to-2 carry-save reduction followed by the new finisher computes the same modular sum. The existing carry-save circuit is unchanged.